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Thang Viet Huynh
(CV updated 22.04.2018)




Biography
Thang Viet Huynh (in Vietnamese: Huỳnh Việt Thắng) was born in Danang, Vietnam in 1980. He received the Eng. degree in Electronics and Telecommunication Engineering in July 2003, and the Master degree in Electronics Engineering in December 2007, both from Danang University of Technology (DUT), Danang, Vietnam. Since October 2003, he has been working as a teaching assistant at the Department of Electronics and Telecommunication Engineering, Danang University of Science and Technology, Danang, Vietnam. From October 2008, he was with the Signal Processing and Speech Communication Laboratory (SPSC) at Graz University of Technology (TU Graz), Graz, Austria, pursuing his PhD study under the supervision of Prof. Gernot Kubin and Dr. Manfred Mücke. In July 2012, he successfully defended his PhD thesis entitled "Efficient Floating-Point Implementation of Signal Processing Algorithms on Reconfigurable Hardware" [available at EURASIP Library of Ph.D. theses]. 



Since August 2012, Dr. Thang  is with the Department of Electronics and Telecommunication Engineering, Danang University of Science and Technology, where he serves as Head of Electronic Division (since Dec. 2012). Currently he is responsible for the courses Digital Circuits and Systems and Selected topics in Electronic Engineering in the undergraduate program specialized in Electronic-Telecommunication Engineering, and the course ASIC Design (with FPGA) for the Master of Electronic Engineering program of the same department. 




Teaching




  • Digital Circuits and Systems (Undergraduate) 
  • Selected topics in Electronic Engineering (Undergraduate)
  • ASIC Design (Master Program)

Research




  • Reconfigurable Embedded Computing (with FPGAs), 
  • Machine Learning and applications
  • Computer arithmetic, Affine Arithmetic and respective applications
  • Network-on-chip (NoC)
Research Project

Contact

HUYNH, Viet Thang, Ph.D. 

Faculty of Electronic and Telecommunication Engineering (ETE), Danang University of Science and Technology (DUT) - The University of Danang, Vietnam. 




E-mail: thanghv@dut.udn.vn  




Publications


[22]. Huỳnh Chỉnh, Huỳnh Việt Thắng, "Ứng dụng học sâu trong hỗ trợ chẩn đoán ung thư da dựa vào hình ảnh", Hội thảo KH quốc gia Công nghệ thông tin & Ứng dụng trong các lĩnh vực (CITA), ISBN 978-604-84-4453-2, trang 155-163, 2019.



[21]. Tuan Nguyen Trong, Nguyen Van Cuong, Thang Viet Huynh, Yen Luong, Hai Dang, "Performance Enhancement of Encryption and Authentication IP cores for IPSec based on Multiple-Core Architecture and Dynamic Partial Reconfiguration on FPGA", SigTelCom 2018 (IEEE), 2018.




[20]. Vu H.M., Thang H.V. (2018), “A Customized Hardware Architecture for Multi-layer Artificial Neural Networks on FPGA”, 4th International Conference on Information Systems Design and Intelligent Applications, Advances in Intelligent Systems and Computing (AISC) Book Series, vol 672, p. 637-644, Springer, Singapore. ISSN:2194-5357. [DOI: https://doi.org/10.1007/978-981-10-7512-4_63].





[19]. Thang Viet Huynh, “Deep Neural Network Accelerator based on FPGA”, in Proceeding of the 4th NAFOSTED Conference on Information and Computer Science (NICS) 2017, IEEE, p. 254-257, Hanoi, Vietnam. [DOI: https://doi.org/10.1109/NAFOSTED.2017.8108073]. 




[18]. Huỳnh Việt Thắng, Huỳnh Minh Vũ, Hồ Phước Tiến, “A framework for customizable deep neural network hardware generation on FPGA”, UDN Journal of Science and Technology, vol. 120 (11.2017), p. 68-71, 2017. ISSN 1859-1531. 




[17]. Thang Viet Huynh, “Evaluation of Artificial Neural Network Architectures for Pattern Recognition on FPGA”, International Journal of Computing and Digital Systems, ISSN: 2210-142X, Vol 6, Issue 3, p. 133-138, 2017. [DOI: http://dx.doi.org/10.12785/ijcds/060305].




[16]. Huỳnh Việt Thắng, “A framework for floating-point bit-width allocation in hardware implementation of signal processing algorithms”, Proc. of the first International Conference on Advanced Technologies in Electrical, Electronic and Communication Engineering (ICATEC) 2016, pp 58-61, 2016.




[15]. Huỳnh Việt Thắng, “Design of Artificial Neural Network Architecture for Handwritten Digit Recognition on FPGA”, UDN Journal of Science and Technology, vol. 108, pp. 290-293, 2016.




[14]. Hồ Anh Trang, Hồ Phước Tiến, Huỳnh Việt Thắng, “An Embedded System for Face Recognition based on Raspberry Pi and Support Vector Machines”, UDN Journal of Science and Technology, vol. 108, pp. 290-293, 2016.




[13]. Trương Văn Trương, Huỳnh Việt Thắng, “Nhận dạng khuôn mặt trên máy tính nhúng Raspberry”, UDN Journal of Science and Technology, vol. 98, no. 1, pp. 122, 2016




[12]. Nguyễn Thị Kim Anh, Nguyễn Trường Thọ, Huỳnh Việt Thắng, “Về một kiến trúc mạng nơ-ron nhân tạo trên FPGA ứng dụng trong nhận dạng chữ số viết tay”, Hội thảo quốc gia về Điện tử, Truyền thông và Công nghệ thông tin năm 2015 (REV-ECIT), ISBN: 978-604-67-0635-9; pp. 253-256, 2015.




[11]. Huynh, Thang Viet, "Design space exploration for a single-FPGA handwritten digit recognition system," 2014 IEEE Fifth International Conference on Communications and Electronics (ICCE), pp.291-296, July 30 2014 - Aug.1 2014.




[10]. Trần Nhật Tin, Lê Thanh Lâm, Huỳnh Việt Thắng, “Implementation of an edge detection module on FPGA”, UDN Journal of Science and Technology, vol. 82, no. 1, pp. 25-28, 2014 (in Vietnamese).




[9]. Huynh Viet Thang, “Hardware cost of reduced precision floating-point neural network architecture of FPGA”, 2nd Intl. Workshop on Industrial IT Convergence (WIITC) 2014, Pages: 45-48, 2014.




[8]. T. V. Huynh and N. H. Anh, "Towards efficient implementation of neural networks with reduced precision Floating-Point parameters," UDN Journal of Science and Technology, vol. 61, no. 1, pp. 105-111, Dec. 2012.




[7]. T. V. Huynh, "On the rounding error of fused multiply-accumulate based floating-point dot-product architectures," UDN Journal of Science and Technology, vol. 61, no. 2, pp. 119-125, Dec. 2012.




[6]. T. V. Huynh, M. Mücke, and W. N. Gansterer, "Evaluation of the stretch s6 hybrid reconfigurable embedded CPU architecture for Power-Efficient scientific computing," Procedia Computer Science, vol. 9, pp. 196-205, Jun. 2012.




[5]. T. V. Huynh and M. Mücke, "Error analysis and precision estimation for floating-point dot-products using affine arithmetic," in The 2011 International Conference on Advanced Technology for Communications (ATC2011).    IEEE, Aug. 2011. 




[4]. T. V. Huynh, M. Mücke, and W. N. Gansterer, "Native double-precision LINPACK implementation on a hybrid reconfigurable CPU," in 18th Reconfigurable Architectures Workshop (RAW 2011).    IEEE, May 2011. 




[3]. T. V. Huynh and M. Mücke, "Exploiting Reconfigurable Hardware to Provide Native Support of Double Precision Arithmetic on Embedded CPUs," in Research Poster Session, International Supercomputing Conference (ISC), Hamburg, Germany, 2010.




[2]. T. V. Huynh and P. N. Nam, "Prototyping of a Network-on-Chip on spartan 3E FPGA," in 2008 Second International Conference on Communications and Electronics.    IEEE, Jun 2008, pp. 24-28.




[1]. T. V. Huỳnh and P. N. Phạm, "Thực hiện Network-on-Chip trên nền FPGA," Tạp chí Khoa học Công nghệ Đại học Đà Nẵng, vol. 22, pp. 19-25, 2007. (in Vietnamese).
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