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 Design of Artificial Neural Network Architecture for Handwritten Digit Recognition on FPGA
Tác giả hoặc Nhóm tác giả: Huỳnh Việt Thắng
Nơi đăng: Tạp chí Khoa học Công nghệ ĐHĐN; Số: 11(108).2016 - Quyển 2;Từ->đến trang: 207-210;Năm: 2016
Lĩnh vực: Khoa học công nghệ; Loại: Bài báo khoa học; Thể loại: Trong nước
TÓM TẮT
This paper presents the design and implementation of a 2 layer feed-forward artificial neural network intellectual property (IP) core applied for handwritten digit recognition system on FPGA. We use 16-bit half-precision floating-point number format to represent the weights of the designed neural network. The neural network is synthesized and verified on Xilinx Virtex-5 XC5VLX-110T, occupies about 41% of FPGA hardware resources and can run at a maximal clock frequency of 205 MHz. When verified on the FPGA board with 10,000 samples from MNIST handwritten digit database, the recognition rate of the designed network is 90.88% and the recognition time is reported as 8 (µs) per sample. Experimental results show that our designed neural network IP core is suitable for embedded pattern recognition applications.
ABSTRACT
This paper presents the design and implementation of a 2 layer feed-forward artificial neural network intellectual property (IP) core applied for handwritten digit recognition system on FPGA. We use 16-bit half-precision floating-point number format to represent the weights of the designed neural network. The neural network is synthesized and verified on Xilinx Virtex-5 XC5VLX-110T, occupies about 41% of FPGA hardware resources and can run at a maximal clock frequency of 205 MHz. When verified on the FPGA board with 10,000 samples from MNIST handwritten digit database, the recognition rate of the designed network is 90.88% and the recognition time is reported as 8 (µs) per sample. Experimental results show that our designed neural network IP core is suitable for embedded pattern recognition applications.
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