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Số người truy cập: 106,842,188

 On the rounding error of fused multiply-accumulate based floating-point dot-product architectures
Tác giả hoặc Nhóm tác giả: Huynh Viet Thang
Nơi đăng: Tạp chí khoa học công nghệ ĐHĐN
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; Số: NA;Từ->đến trang: NA;Năm: 2012
Lĩnh vực: Kỹ thuật; Loại: Bài báo khoa học; Thể loại: Trong nước
TÓM TẮT
This paper focuses on the rounding error analysis using affine arithmetic (AA) and bit width allocation of floating-point (FP) dot-product implementations on reconfigurable hardware for advanced digital signal processing applications. An AA-based rounding error model for the fused multiply-accumulate (FMA) operation is, for the first time, suggested in this paper. Using the proposed error model, we then both experimentally and analytically investigate the rounding error of the FMA-based FP dot-product implementation. It is surprisingly shown that the overall rounding error of a floating-point dot-product implementation can significantly be improved by employing a parallel architecture, rather than by employing an FMA. Additionally, the analytical rounding error models for all floating-point dot-product architectures are derived, allowing for an efficient design space exploration and which are the keys to specialised code generators.
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ABSTRACT
This paper focuses on the rounding error analysis using affine arithmetic (AA) and bit width allocation of floating-point (FP) dot-product implementations on reconfigurable hardware for advanced digital signal processing applications. An AA-based rounding error model for the fused multiply-accumulate (FMA) operation is, for the first time, suggested in this paper. Using the proposed error model, we then both experimentally and analytically investigate the rounding error of the FMA-based FP dot-product implementation. It is surprisingly shown that the overall rounding error of a floating-point dot-product implementation can significantly be improved by employing a parallel architecture, rather than by employing an FMA. Additionally, the analytical rounding error models for all floating-point dot-product architectures are derived, allowing for an efficient design space exploration and which are the keys to specialised code generators.
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