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 Design space exploration for a single-FPGA handwritten digit recognition system
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Tác giả hoặc Nhóm tác giả: Thang Viet Huynh
Nơi đăng: in Proc. of IEEE ICCE-2014 "The 5th International Conference on Communications and Electronics"
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; Số: NA;Từ->đến trang: 291-296;Năm: 2014
Lĩnh vực: Kỹ thuật; Loại: Bài báo khoa học; Thể loại: Quốc tế
TÓM TẮT
Multilayer perceptron neural networks have widely been implemented on reconfigurable hardware to perform a variety of applications including classification and pattern recognition. This paper investigates the combined impact of neural network size and reduced precision number formats, used for the representation of the optimal parameters, on the recognition rate a neural network based handwritten digit recognition system. The MNIST database is used for training and testing in this work. After deriving the optimal reduced-precision floating-point format sufficient for achieving a desired recognition performance, we provide an estimate for the hardware resources needed to implement the network on FPGAs. Our work allows for an efficient investigation of tradeoffs in operand word-length, network size, recognition rate and hardware cost of reduced-precision neural network implementations on reconfigurable hardware.
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ABSTRACT
Multilayer perceptron neural networks have widely been implemented on reconfigurable hardware to perform a variety of applications including classification and pattern recognition. This paper investigates the combined impact of neural network size and reduced precision number formats, used for the representation of the optimal parameters, on the recognition rate a neural network based handwritten digit recognition system. The MNIST database is used for training and testing in this work. After deriving the optimal reduced-precision floating-point format sufficient for achieving a desired recognition performance, we provide an estimate for the hardware resources needed to implement the network on FPGAs. Our work allows for an efficient investigation of tradeoffs in operand word-length, network size, recognition rate and hardware cost of reduced-precision neural network implementations on reconfigurable hardware.
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